I currently work on two research topics:
- High Level Synthesis of Digital Circuits Porjects for FPGA Co-Processing
- The Kiwi project with David Greaves which synthesizes circuits from high level circuit models written using regular multi-threaded code in languages like C#.
- Synthesis of C programs that manipulate dynamic data structurs in the heap.
- Synthesis of data-parallel programs in C++ and C# into FPGAs for co-processing.
- High level techniques for designing low level circuits. I have re-implemented my Lava system in C# and F# and I have made HLINQ which is a circuit generator for LINQ queries.
- Evaluation and experimentation with alternative hardware description techniques with a focus on Bluespec and Esterel.
- Concurrent and Parallel Programming in Haskell
- Specifically, I have been working on the ThreadScope profiler to help understand the behavior of parallel and concurrent Haskell programs.
I have served on several programme committees including FCCM, FPGA, FPL, FPT, DATE, FMCAD, DCC, HFL, DAMP, and Memocode. I chaired the system level modeling track for DATE for three years and I currently serve on the high level synthesis track committee. I am also a member of IFIP Working Group 2.8 on functional programming. I am a visiting lecturer at Chalmers. I have over 50 publications some of which are shown below.
I am co-chairing The Programming Challenge of Heterogeneous Architectures workshop at the School of Computer Science, Birmingham University, 2-3 July 2009.
- Simon Marlow, Simon Peyton Jones, and Satnam Singh, Runtime Support for Multicore Haskell, in ICFP 2009, Association for Computing Machinery, Inc., 5 September 2009
- Don Jones Jr., Simon Marlow, and Satnam Singh, Parallel Performance Tuning for Haskell, in ACM SIGPLAN 2009 Haskell Symposium, Association for Computing Machinery, Inc., 3 September 2009
- Byron Cook, Ashutosh Gupta, Stephen Magill, Andrey Rybalchenko, Jiří Šimša, Satnam Singh, and Viktor Vafeiadis, Finding heap-bounds for hardware synthesis, in Submitted for publication., 8 June 2009
- Satnam Singh, Satnam Singh. Design and Verification of Peripheral Control Circuits in Esterel, in Journal of Concurrency and Computation., Wiley, 5 May 2009
- Satnam Singh and Simon Peyton Jones, A Tutorial on Parallel and Concurrent Programming in Haskell, in Advanced Functional Programming Summer School 2008, Springer Verlag, Nijmegen, Holland, May 2009
- David J. Greaves and Satnam Singh, Exploiting System-Level Concurrency Abstractions for Hardware Descriptions, no. MSR-TR-2009-48, 22 April 2009
- Satnam Singh, A Bluespec Implementation of an FPGA-based Photoshop Plug-In, in HFL 2009., 28 March 2009
- Satnam Singh, David Greaves, and Sutirtha Sanyal, Synthesis of a Parallel Smith-Waterman Sequence Alignment Kernel into FPGA Hardware, in Many-Core and Reconfigurable Supercomputing Conference 2009, Berlin., March 2009
- David Greaves and Satnam Singh, Application Specific Circuits with Concurrent C# Programs, in Draft under submission to a conference., 5 February 2009
- Byron Cook, Ashutosh Gupta, Satnam Singh, and Viktor Vafeiadis, Gate Synthesis for C Programs with Heap, in Draft under submission., 7 January 2009
- David Greaves and Satnam Singh, Using C# Attributes to Describe Hardware Artefacts within Kiwi, in Specification and Design Languages Forum (FDL) 2008., IEEE Computer Society, September 2008
- Stephen Edwards, Satnam Singh, and Nalini Vasudevan, A Deterministic Multi-Way Rendezvous Library for Haskell, in IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE Computer Society, April 2008
- David Greaves and Satnam Singh, Kiwi: Synthesis of FPGA Circuits from Parallel Programs, in IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), IEEE Computer Society, April 2008
- David Greaves and Satnam Singh, Describing Hardware with Parallel Programs, in Designing Correct Circuits, Budapest, 2008., March 2008
- Satnam Singh, Specifying Circuit Layout on FPGAs, in Reconfigurable Computing, Morgan Kaufmann Publishers, 2008
- Satnam Singh, Declarative Programming Techniques for Many-Core Architectures., in Workshop on Hardware Design and Functional Languages, 2007
- Tim Harris and Satnam Singh, Feedback-directed implicit parallelism, in Proceedings of ICFP 2007 (to appear), January 2007
- Satnam Singh, Hardware/Software Syntheiss and Verification using Esterel, in Communicating Process Architectures, 2007
- Satnam Singh, Digital CAD Tools as Transactional Memory Workloads, in Workshop on Transactional Memory Workloads, June 2006
- Anthony Discolo, Tim Harris, Simon Marlow, Simon Peyton-Jones, and Satnam Singh, Lock Free Data Structures using STMs in Haskell, in FLOPS '06: Proceedings of the Eighth International Symposium on Functional and Logic Programming, to appear, April 2006
- Gerogio Chrysanthakopoulos and Satnam Singh, An Asynchronous Messaging Library for C#, in Synchronization and Coordination in Object Orientated Lanugaes, October 2005
- Satnam Singh, Designing Reconfigurable Systems in Lava, in VLSI Design 2004, 2004
- Satnam Singh, A Demonstration of Co-Design and Co-Verification in a Synchronous Language. Design, in Design, Automation and Test in Europe, IEEE Computer Society, 2004
Some Recent Talks
- C-to-Gates Stnthesis of Dynamic Data Structures. Practical Synthesis for Concurrent Systems (PSY) 2009, Grenoble (CAV workshop). 28 June 2009.
- Three Approaches to High Level Synthesis. IBM Zurich Research Lab. 17 June 2009.
- GPU Programming with Microsoft Accelerator. Oxford University. 5 June 2009.
- Pointer Synthesis++. UK Design Forum '09. 8 May 2009.
- An Overview of Parallel and Concurrent Programming in Haskell. Unviersity of Leeds. 30 April 2009.
- Kiwi: Synthesis of FPGA Cicuits from Multi-Threaded C# Programs. European Bioinfomatics Instiute and Sanger. 29 April 2009.
- Kiwi: Synthesis of FPGA Cicuits from Multi-Threaded C# Programs. Cadence Research Labs. 7 April 2009.
- Bluespec Experience Report. HFL 2009. 28 March 2009. Also at Xilinx on 3 April 2009.
- Kiwi: Synthesis of FPGA Circuits from Multi-Threaded C# Programs. Presentation at Southampton University. 28 January 2009.
- An Overview of Parallel and Concurrent Programming in Haskell. Presentation at Southampton University. 28 January 2009.
- Kiwi: Automatic Synthesis of Parallel Programs into FPGA Circuits. Seminar at ETH Zurich. 3 November 2008. Also talks at Chalmers, BSC, and BCS.
- Challenges of programming multi-core microprocessors. Keynote talk. IET Programmable Hardware Systems 2008.
- Synthesizing FPGA Circuits from Parallel Programs. Keynote talk at ARC 2008.
- An Overview of Parallel and Concurrent Programming in Haskell. At Stanford, Kent and Herriot-Watt.
- Programming Models for Reconfigurable Systems. Keynote talk. IET FPGA Developers' Forum. 30 October 2007.
- Programming Models for Reconfigurable Systrems. Invited talk at the UK Design Forum. 2008.
- Programming Models for Reconfigurable Systems. Keynote talk at RAW 2007.
- New Directions in Parallel Programming. Invited talk cat CSAW 2007.
- Lava. Invited talks at Nottingham, Birmingham and Freiburg. 2007
Bio
Satnam Singh's research involves finding novel ways to program and use special Lego-like chips called FPGAs. In particular, he is interested in making the circuits on these chips change as they run to adapt to new situations. Satnam Singh completed his PhD at the University of Glasgow in 1991 where he devised a new way to program and analyze digital circuits described in a special functional programming language. He then went on to be an academic at the same university (first in the Electrical Engineering department and then in the Computing Science department) and lead several research projects that explored novel ways to exploit FPGA technology for applications like software radio, Adobe Photoshop and high resolution digital printing, and graphics. In 1998 he moved to San Jose California to join Xilinx's research lab where we developed more tools and technology for designing and formally verifying circuits for FPGAs as well as the actual FPGA chips. In particular, he developed a language called Lava in conjunction with Chalmers University which allows circuits to be laid out nicely on chips to give high performance and better utilization of silicon resources. In 2004 he joined Microsoft in Redmond Washington where we worked on a variety of techniques for producing concurrent and parallel programs and in particular explored join patterns and software transactional memory. In 2006 he moved to Microsoft's research laboratory in Cambridge where he works on reconfigurable computing and parallel functional programming.
