I am a researcher at Microsoft's Cambridge UK lab and I also hold the Chair of Reconfigurable Systems at the University of Birmingham. I currently work on two research topics:

• Alchemy: Transmuting Programs into Circuits for computing with reduced latency or energy consumption.  
  • The compilation of data-parallel programs written in C++ and .NET langauges like C# into FPGA circuits.
  • The Kiwi project with David Greaves which synthesizes circuits from high level circuit models written using regular multi-threaded code in languages like C#.
  • Synthesis of C programs that manipulate dynamic data structurs in the heap.
  • Synthesis of data-parallel programs in C++, C#  and F# written with using the Microsoft Accelerator V2 library into FPGAs for co-processing.
  • High level techniques for designing low level circuits. I have re-implemented my Lava system in C# and F# and I have made HLINQ which is a circuit generator for LINQ queries.
  • Evaluation and experimentation with alternative hardware description techniques with a focus on Bluespec and Esterel.
• Concurrent and Parallel Programming in Haskell for exploiting the potential of pure functional programming for exploiting parallel computing resources in a civilized manner. 
  • Specifically, I have been working on the ThreadScope profiler to help understand the behavior of parallel and concurrent Haskell programs.
  • Higher level data-parallel programming models based on Accelerator.
  • The compilation of recursive Haskell funcitons into circuits.
• Current conference and workshop organization:
  • FCCM 2012: PC chair.
  • FMCAD 2012: PC co-chair.
  • FPL 2012: PC co-chair.
  • CCPC 2012: Workshop on compiling complete programs into circuits (at ASPLOS 2012): co-chair.

Previosuly I was on the programme committee for First Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010) . I also co-chaired the First European NetFPGA Developers Workshop (EURODEV) in Cambridge. I was also the publicity chair for FPGA 2011 and the general chair and finance chair for MEMOCODE 2011. I also co-organized the DATE 2011 workshop called Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.

I have served on several programme committees including the POPL ERC, ICFP, FCCM, FPGA, FPL, FPT, DATE, FMCAD, DCC, HFL, DAMP, CARL, CHANGE and HEART. I chaired the system level modeling track for DATE for three years and I serve on the high level synthesis track committee. I am also a member of IFIP Working Group 2.8 on functional programming. I am a visiting professor at the department of electronics and electrical engineering at Imperial College in London; I am a visiting lecturer at Chalmers in Gothenberg Sweden; and I am a fellow of the IET and I am a Senior Member of the IEEE and the ACM. I have over 80 publications some of which are shown below.

I have an MSDN blog which currently discussed GPGPU and x64 SIMD multicore programming from F# and C# and well as practical aspects of programming in Haskell.

Email: satnams@microsoft.com
Phone: +44 1223 479905
UK cell: +44 7979 648412. USA cell: +1 206 330 1580
Address: Microsoft, 7 JJ Thomson Avenue, Cambridge, CB3 0FB, United Kingdom.

Bio

Satnam Singh's research interests include involves finding novel ways to program and use reconfigurable chips called FPGAs and in parallel functional programming. Satnam Singh completed his PhD at the University of Glasgow in 1991 where he devised a new way to program and analyze digital circuits described in a special functional programming language. He then went on to be an academic at the same university and lead several research projects that explored novel ways to exploit FPGA technology for applications like software radio, image processing and high resolution digital printing, and graphics. In 1998 he moved to San Jose California to join Xilinx's research lab where he developed a language called Lava in conjunction with Chalmers University which allows circuits to be laid out nicely on chips to give high performance and better utilization of silicon resources. In 2004 he joined Microsoft in Redmond Washington where we worked on a variety of techniques for producing concurrent and parallel programs and in particular explored join patterns and software transactional memory. In 2006 he moved to Microsoft's research laboratory in Cambridge where he works on reconfigurable computing and parallel functional programming. He holds the Chair of Reconfigurable Systems at the University of Birmingham; is a Fellow of the IET; a Senior Member of the IEEE and ACM; a visiting professor at Imperial College; and a visiting lecturer at Chalmers in Gothenburg, Sweden.