Ray Bittner
Source code for "The Speedy DDR2 Controller For FPGAs," as presented at ERSA 2009, can be found here. Now updated to version 1.1 with several improvements and bug fixes.
Source code for "Bus Mastering PCI Express In An FPGA", as presented at FPGA 2009, can be found here.
Source code for the much faster "Speedy Bus-Mastering PCI Express", as presented at FPL 2012, can be found here.
If you have any questions, comments, suggestions, I can be reached at raybit@microsoft.com.
Publications
- Ray Bittner, Erik Ruf, and Alessandro Forin, Direct GPU/FPGA Communication Via PCI Express, in Cluster Computing, Springer Verlag, 17 May 2013
- Ray Bittner and Erik Ruf, Direct GPU/FPGA Communication Via PCI Express, in 1st International Workshop on Unconventional Cluster Architectures and Applications (UCAA 2012), 10 September 2012
- Ray Bittner, Speedy Bus Mastering PCI Express, in 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), 29 August 2012
- Jason Oberg, Ken Eguro, Ray Bittner, and Alessandro Forin, Random Decision Tree Body Part Recognition Using FPGAs, in International Conference on Field Programmable Logic and Applications , August 2012
- Mahsan Rofouei, Mike Sinclair, Ray Bittner, Tom Blank, Nick Saw, Gerald DeJean, and Jeff Heffron, A Non-invasive Wearable Neck-cuff System for Real-time Sleep Monitoring, IEEE Computer Society, May 2011
- Ji Sun, Ray Bittner, and Ken Eguro, FPGA Side-Channel Receivers, in International Symposium on Field-Programmable Gate Arrays (Best Paper Award - Honorable Mention), February 2011
- Ray Bittner and Mike Sinclair, VersaPatch A Low Cost 2.5D Capacitive Touch Sensor, in Proceedings Of HCI 2009, 24 July 2009
- Ray Bittner, The Speedy DDR2 Controller For FPGAs, in Proceedings Of ERSA 2009, 13 July 2009
- Ray Bittner, Bus Mastering PCI Express In An FPGA, Association for Computing Machinery, Inc., 23 February 2009
- Turner Whitted, Jim Kajiya, Erik Ruf, and Ray Bittner, Embedded Function Composition, in Proceedings of the Conference on High Performance Graphics 2009, Association for Computing Machinery, Inc., 2009
- Ray Bittner, Overcoming Memory Latency And Enabling Parallelism With The Greedy CAM Architecture, January 2007
- Lin Zhong, Mike Sinclair, and Ray Bittner, A Phone-centered body sensor network platform: Cost, energy efficiency & user interface, in Proceedings of the International Workshop on Body Sensor Networks, Institute of Electrical and Electronics Engineers, Inc., April 2006
- Ray Bittner and Peter Athanas, Computing Kernels Implemented With A Wormhole RTR CCM, in 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), IEEE, April 1997
- Ray Bittner and Peter Athanas, Wormhole Run-time Reconfiguration, in Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays, Association for Computing Machinery, Inc., 1997
- Ray Bittner, Mark Musgrove, and Peter Athanas, Colt: An Experiment in Wormhole Run-Time Reconfiguration, in Photonics East Conference on High-Speed Computing, Digital Signal Processing, and Filtering Using FPGAs, 21 October 1996
