Share on Facebook Tweet on Twitter Share on LinkedIn Share by email
Ray Bittner

Source code for "The Speedy DDR2 Controller For FPGAs," as presented at ERSA 2009, can be found here.  Now updated to version 1.1 with several improvements and bug fixes.

Source code for "Bus Mastering PCI Express In An FPGA", as presented at FPGA 2009, can be found here.

Source code for the much faster "Speedy Bus-Mastering PCI Express", as presented at FPL 2012, can be found here.

If you have any questions, comments, suggestions, I can be reached at