John was previously a member of Stanford's Hydra research group, which investigated a thread-level speculative Single-Chip Multiprocessor. John completed his PhD in Electrical Engineering at Stanford University at the end of 2006. His research focused on building a Flexible Architecture for Simulation and Testing, FAST . His dissertation describes the hardware and software required to build a reconfigurable prototyping platform focused on implementing computer architectures with novel memory system designs like Hydra or other thread-level parallel architectures. There is a brief description of FAST available on Wikipedia if reading a dissertation is not your thing.
John received his BS in Computer Science and Engineering from the University of Washington in 1997. He later spent two years as a faculty research assistant for the Computer Science department at the University of Maryland in College Park. Simultaneoulsy, John worked on various bioinformatics projects at Johns Hopkins Medical Institute for the Department of Pathology. John was awarded his MS in Electrical Engineering from Stanford with an emphasis in Compilers and Digital Circuit Design in 2001. John also spent three years working in the Niagara Architecture Performance Group for Sun Microsystems from 2003-2006.
John is a Researcher in Microsoft Research's Silicon Valley lab, which he joined in March, 2007. His widely varied research interests include computer architecture, embedded systems, application behavior and performance tuning, and hardware-software co-design and interaction.
- Hari Kannan, Mihai Budiu, John D. Davis, and Girish Venkataramani, Tuning SoCs using the Global Dynamic Critical Path, in the Proceedings of the 22nd IEEE International SOC Conference (SOCC), IEEE, September 2009
- Abhishek Rajimwale, Vijayan Prabhakaran, and John D. Davis, Block Management in Solid-State Devices, in Proceedings of the USENIX Annual Technical Conference (USENIX'09), USENIX, June 2009
- Hari Kannan, Mihai Budiu, John D. Davis, and Girish Venkataramani, Tuning SoCs using the Dynamic Critical Path, no. MSR-TR-2009-44, 20 April 2009
- John D. Davis, Charles P. Thacker, and Chen Chang, BEE3: Revitalizing Computer Architecture Research, no. MSR-TR-2009-45, April 2009
- John D. Davis and Lintao Zhang, FRP: a Nonvolatile Memory Research Platform Targeting NAND Flash, in The First Workshop on Integrating Solid-state Memory into the Storage Hierarchy, Held in Conjunction with ASPLOS 2009, Association for Computing Machinery, Inc., March 2009
- Martha Mercaldi Kim, John D. Davis, Mark Oskin, and Todd Austin, Polymorphic On-Chip Networks, in International Symposium on Computer Architecture (ISCA-35), Institute of Electrical and Electronics Engineers, Inc., June 2008
- Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy, Design Tradeoffs for SSD Performance, in Proceedings of the 2008 USENIX Technical Conference (USENIX'08), USENIX, June 2008
- John D. Davis, Zhangxi Tan, Fang Yu, and Lintao Zhang, A Practical Reconfigurable Hardware Accelerator for Boolean Satisfiability Solvers, in 45th Design Automation Conference, Association for Computing Machinery, Inc., June 2008
- John D. Davis, Zhangxi Tan, Fang Yu, and Lintao Zhang, Designing an Efficient Hardware Implication Accelerator for SAT Solving, in International Conference on Theory and Applications of Satisfiability Testing (SAT), Springer, Guangzhou, China, May 2008



