I am a researcher in the Computer Architecture Group at Microsoft Research (MSR). My research interests are in the broad area of computer architecture, with an emphasis on multicore architectures, hardware-sofware interaction, and the application of machine learning to computer systems.

I received my B.S. (2003), M.S. (2007), and Ph.D. (2008) degrees in Electrical and Computer Engineering from Cornell University, where I was a member of the M3 research group and the Computer Systems Laboratory (CSL). For my Ph.D. dissertation, I explored Reconfigurable and Self-Optimizing Multicore Architectures, multicore systems that can adapt both their internal hardware organization and their resource management and control policies to the needs of the software products executing on them.

Research Projects

• Self-Optimizing Multicore Architectures
• Dynamically Reconfigurable Multicore Architectures
• Efficient Architectural Design Space Exploration Using Machine Learning
• Novel Memory-System Technologies

Professional Activities

• Conference Program Committee Member: MICRO'09, ICCD'09.
• Conference Organizing Committee Member: IISWC'08 (publication chair).
• Workshop Program Committee Member: SMART'10 (with HiPEAC)
• Workshop Co-organizer: NDCA'09 (with MICRO), EAMA'09 (with HPCA).
• Review Panel Member: NSF-SHF'09.

Interns

• Janani Mukundan, Cornell University, Summer 2009.
• Ramazan Bitirgen, Cornell University, Spring 2008.
• Biplab Deka, IIT Kanpur, Summer 2008.

Fully Refereed Archival Publications

• Better I/O Through Byte-Addressable, Persistent Memory [SOSP'09]
  J. Condit, E. Nightingale, C. Frost, E. İpek, D. Burger, B. Lee, and D. Coetzee.
  In Symp. on Operating Systems Principles, Big Sky, MT, October 2009.
• Architecting Phase-Change Memory as a Scalable DRAM Alternative [ISCA'09]
  B. Lee, E. İpek, O. Mutlu, D. Burger.
  In Intl. Symp. on Computer Architecture, Austin, TX, June 2009.
• Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach [MICRO'08]
  R. Bitirgen, E. İpek, and J.F. Martínez.
  In Intl. Symp. on Microarchitecture, Lake Como, Italy, November 2008.
• Self-Optimizing Memory Controllers: A Reinforcement Learning Approach [ISCA'08]
  E. İpek, O. Mutlu, J.F. Martínez, and R. Caruana.
  In Intl. Symp. on Computer Architecture, Beijing, China, June 2008.
• Efficient Architectural Design Space Exploration via Predictive Modeling [TACO'08]
  E. İpek, S.A. McKee, K. Singh, R. Caruana, B.R. de Supinski, M. Schulz.
  In ACM Transactions on Architecture and Code Optimization, January 2008.
• Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor [DSN'07]
  C.C. LaFrieda, E. İpek, J.F. Martínez, and R. Manohar.
  In Intl. Conf. on Dependable Systems and Networks, Edinburgh, Scotland, June 2007.
• Core Fusion: Accommodating software diversity in chip multiprocessors [ISCA'07]
  E. İpek, M. Kırman, N. Kırman, and J.F. Martínez.
  In Intl. Symp. on Computer Architecture, San Diego, CA, June 2007.
  _{^{Earlier version appears in Workshop on Complexity-Effective Design, conc. with ISCA, June 2006.}}
• Efficiently Exploring Architectural Design Spaces via Predictive Modeling [ASPLOS'06]
  E. İpek, S.A. McKee, B.R. de Supinski, M. Schulz, R. Caruana.
  In Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October 2006.
• An Approach to Performance Prediction for Parallel Applications [EURO-PAR'05]
  E. İpek, B.R. de Supinski, M. Schulz, S.A. McKee.
  In Intl. European Conf. on Parallel Computing, Lisbon, Portugal, August 2005.

Last Update: July 2009.