Eric Chung

RESEARCHER
erchung "at" microsoft.com

112/3376, 1-650-693-3980 x33980

Curriculum vita 

I am a Researcher in the Microsoft Research Technologies (MSR-T) lab.  I am a member of the Catapult team and am broadly interested in the application, programmability, and design of specialized hardware (such as FPGAs) in the datacenter. I received my PhD at Carnegie Mellon in 2011 and my BS in EECS at UC Berkeley in 2004.

Selected Publications

Service

  • Program committees - ASBD'14, FCCM'14, SBAC-PAD'14, CARL'13, FCCM'13, FCCM'12
  • External committees - MICRO'14, MICRO'12
  • External reviewer - MICRO, HPCA, ASPLOS, FCCM, TRETS, CARL, CASES, HIPEAC, TPDS
  • Publications Chair - ISCA'14

Selected Talks and Tutorials

  • RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-Gold
    Held in conjunction with ISPASS-2010, March 28, 2010.
  • Open Source Protoflex Simulator
    RAMP summer retreat at UT Austin, Austin, TX, 6/09.
  • Accelerating Architectural-Level Full-System Simulations Using FPGAs
    Guest speaker at Microsoft Research, Redmond, CA, 10/07.
  • Architectural Emulation on FPGAs Made Easy with Bluespec
    1st Bluespec Workshop at MIT, Boston, MA, 8/07.
  • Combining Simulators and FPGAs: "An Out-of-Body Experience"
    RAMP summer retreat at MIT, Boston, MA, 6/06.