I am a Researcher in the Microsoft Research Technologies (MSR-T) lab. I am a member of the Catapult team and am broadly interested in the application, programmability, and design of specialized hardware (such as FPGAs) in the datacenter. I received my PhD at Carnegie Mellon in 2011 and my BS in EECS at UC Berkeley in 2004.
- A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
Andrew Putnam, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James R. Larus, Eric Peterson, Gopi Prashanth, Aaron Smith, Jason Thong, Phillip Yi Xiao, and Doug Burger. 41st Annual International Symposium on Computer Architecture (ISCA), Minneapolis, MN, June 2014.
- A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication
Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric Chung, and Greg Stitt. 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014.
- AN3: A Low-Cost Circuit-Switched Datacenter Network
Eric S. Chung, Andreas Nowatzyk, Tom Rodeheffer, Chuck Thacker, Fang Yu. Microsoft Technical Report, MSR-TR-2014-35.
- LINQits: Big Data on Little Clients
Eric S. Chung, John D. Davis, and Jaewon Lee. 40th International Symposium on Computer Architecture, Tel-Aviv, Israel, June 2013.
- ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects
Eric S. Chung and Michael K. Papamichael. 21st International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, April 2013.
- Towards a Universal FPGA Matrix-Vector Multiplication Architecture
Srinidhi Kestur, John D. Davis, and Eric S. Chung. 20th IEEE International Symposium on Field-Programmable Custom Computing Machines, Toronto, Canada, April 2012.
- Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing
Eric S. Chung, Michael K. Papamichael, Gabriel Weisz, James C. Hoe, and Ken Mai. 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2012.
- CoRAM: An In-Fabric Memory Abstraction for FPGA-based Computing
Eric S. Chung, James C. Hoe, and Ken Mai. 19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2011.
(* Best paper award *)
- Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPUs? [Slides]
Eric S. Chung, Peter A. Milder, James C. Hoe, and Ken Mai. International Symposium on Microarchitecture (MICRO-43), Atlanta, GA, 2010.
- High-Level Design and Validation of the BlueSPARC Multithreaded Processor
Eric S. Chung and James C. Hoe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.10, pp.1459-1470, Oct. 2010.
- Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation
Eric S. Chung and James C. Hoe. Formal Methods and Models for Codesign (MEMOCODE), Boston, MA, 2009.
- ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. ACM Transactions on Reconfigurable Technology and Systems, 2009.
- A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2008.
- Virtualized Full-System Emulation of Multiprocessors using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.
2nd Workshop on Architectural Research Prototyping in conjunction with the 34th International Symposium on Computer Architecture, San Diego, June 2007.
- Co-Simulation for Component-wise FPGA Emulator Development
Eric S. Chung, James C. Hoe, and Babak Falsafi. Workshop on Architecture Research using FPGA Platforms, 11th International Symposium on High-Performance Computer Architecture, Austin, TX, February 12, 2006.
- Program committees - ASBD'14, FCCM'14, SBAC-PAD'14, CARL'13, FCCM'13, FCCM'12
- External committees - MICRO'14, MICRO'12
- External reviewer - MICRO, HPCA, ASPLOS, FCCM, TRETS, CARL, CASES, HIPEAC, TPDS
- Publications Chair - ISCA'14
Selected Talks and Tutorials
RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-Gold
Held in conjunction with ISPASS-2010, March 28, 2010.
Open Source Protoflex Simulator
RAMP summer retreat at UT Austin, Austin, TX, 6/09.
Accelerating Architectural-Level Full-System Simulations Using FPGAs
Guest speaker at Microsoft Research, Redmond, CA, 10/07.
Architectural Emulation on FPGAs Made Easy with Bluespec
1st Bluespec Workshop at MIT, Boston, MA, 8/07.
Combining Simulators and FPGAs: "An Out-of-Body Experience"
RAMP summer retreat at MIT, Boston, MA, 6/06.