I joined as a Post-doc Researcher in Microsoft Research's Silicon Valley Lab in September 2011. I am broadly interested in the scalability and programmability of future, energy-efficient computer architectures, spanning mobile devices to datacenter-scale computers. My goals are to: (1) identify and expand the role of specialized logic in future systems, and (2) enable hardware specialization “for the masses” by improving the architecture, portability, programmability, and debuggability of future, hardware-based accelerators. I am also interested in FPGA architectures, FPGA-based full-system prototyping methodologies, analytical modeling of heterogeneous multicores, and tools for automated hardware generation and designer productivity.
I received my BS in Electrical Engineering and Computer Science from the University of California, Berkeley in 2004. I then joined the Computer Architecture Lab at Carnegie Mellon University and completed my PhD in 2011 under the supervision of James Hoe.
- 3/6/2013: Our paper titled "LINQits: Big Data on Little Clients" was accepted to ISCA'13!
- 2/23/2013: Our paper titled "ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects" was accepted to FCCM'13!
- 1/16/2013: Download our efficient ZYNQ AXI mastering interface: single-port, quad-port
- 3/1/2012: Our paper titled "Towards a Universal FPGA Matrix-Vector Multiplication Architecture" was accepted to FCCM'12!
- 2/27/2012: Try out the CoRAM architecture in the browser!
- 2/22/2012: I will be attending FPGA'12 (Preliminary Program)
- 1/16/2012: I will be serving on the program committee for FCCM'12 (CFP)
- 11/23/2011: Our paper on the prototype and evaluation of CoRAM was accepted to FPGA'12!
- LINQits: a hardware-software framework for accelerating LINQ queries in C#, currently targeting future mobile systems-on-chips (SoC) with reconfigurability
- Connected RAM (CORAM): an effort to develop portable, high-performance memory systems for FPGA-based computing (active)
- BLAS Acceleration: Towards A Universal FPGA-Based Library for Matrix Algebra
- B3RISC: development of a low-cost soft core for prototyping the Singularity OS on the BEE3
- ProtoFlex: a project to accelerate full-system, multiprocessor simulations by virtualizing the ISA behaviors and core counts across limited FPGA resources
- RAMP: a multi-university effort to develop and promote FPGA-based multiprocessor emulation and prototyping
- TRUSS: a project to develop a reliable, available, and serviceable (RAS) hardware platform using commodity blade components
- GUIR: group for user-interface research at UC Berkeley
- LINQits: Big Data on Little Clients
Eric S. Chung, John D. Davis, and Jaewon Lee. To appear in 40th International Symposium on Computer Architecture, Tel-Aviv, Israel, June 2013.
- ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects
Eric S. Chung and Michael K. Papamichael. To appear in 21st International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, April 2013.
- Towards a Universal FPGA Matrix-Vector Multiplication Architecture
Srinidhi Kestur, John D. Davis, and Eric S. Chung. To appear in 20th IEEE International Symposium on Field-Programmable Custom Computing Machines, Toronto, Canada, April 2012.
- Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing
Eric S. Chung, Michael K. Papamichael, Gabriel Weisz, James C. Hoe, and Ken Mai. 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2012.
- CoRAM: An In-Fabric Memory Abstraction for FPGA-based Computing
Eric S. Chung, James C. Hoe, and Ken Mai. 19th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2011.
(* Best paper award *)
- Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPUs? [Slides]
Eric S. Chung, Peter A. Milder, James C. Hoe, and Ken Mai. International Symposium on Microarchitecture (MICRO-43), Atlanta, GA, 2010.
- High-Level Design and Validation of the BlueSPARC Multithreaded Processor
Eric S. Chung and James C. Hoe. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.10, pp.1459-1470, Oct. 2010.
- Implementing a High-performance Multithreaded Microprocessor:
A Case Study in High-level Design and Validation
Eric S. Chung and James C. Hoe. Formal Methods and Models for Codesign (MEMOCODE), Boston, MA, 2009.
- ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations
Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. ACM Transactions on Reconfigurable Technology and Systems, 2009.
- A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2008.
- Virtualized Full-System Emulation of Multiprocessors using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.
2nd Workshop on Architectural Research Prototyping in conjunction with the 34th International Symposium on Computer Architecture, San Diego, June 2007.
- Co-Simulation for Component-wise FPGA Emulator Development
Eric S. Chung, James C. Hoe, and Babak Falsafi. Workshop on Architecture Research using FPGA Platforms, 11th International Symposium on High-Performance Computer Architecture, Austin, TX, February 12, 2006.
Selected Talks and Tutorials
RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-Gold
Held in conjunction with ISPASS-2010, March 28, 2010.
Open Source Protoflex Simulator
RAMP summer retreat at UT Austin, Austin, TX, 6/09.
Accelerating Architectural-Level Full-System Simulations Using FPGAs
Guest speaker at Microsoft Research, Redmond, CA, 10/07.
Architectural Emulation on FPGAs Made Easy with Bluespec
1st Bluespec Workshop at MIT, Boston, MA, 8/07.
Combining Simulators and FPGAs: "An Out-of-Body Experience"
RAMP summer retreat at MIT, Boston, MA, 6/06.