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Prior to MSR

Ken Eguro

One Microsoft Way
Redmond, WA 98052


Research Projects

CAD Algorithms for Pipelined Netlists

Heavily registered applications confuse classical FPGA packing, retiming, placement, and routing tools. We investigated the causes of these troubles and proposed new timing-driven, register-aware approaches. The CAD portion of my dissertation shows how these tools can relate to each other.


  • Provisional US Patent #4178-Inv-0001P.1USPRO, Enhancing Timing-Driven Placement


Domain-Specialized FPGAs

The adaptability of FPGAs make them very attractive for use in many types of hardware systems. However, the overhead required to implement this flexibility is a source of area/power/performance penalties. Can we reduce this overhead by looking at the applications we expect run on the FPGA and specialize the architecture for these domains?


Routing-Aware Placement

Classical placement algorithms for both standard VLSI and FPGA designs rely heavily on total wirelength cost. However, this cost model cannot account for routing congestion or asymmetry in routing resources. In somewhat of a chicken & egg problem, system designers only develop very specific (and potentially wasteful) types of architectures - mislead by the results of insufficient CAD tools. We investigated possible ways to fix these issues.



The compilation process to produce FPGA circuits is often very time consuming. For certain types of applications and for very large designs, conventional tools can simply be too slow. We looked at various ways to speed the process.

Book Chapter


  • X. Yang, M. Wang, K. Eguro, and M. Sarrafzadeh, "A Snap-On Placement Tool", ACM International Symposium on Physical Design, 2000, 153-58.