One Microsoft Way
Redmond, WA 98052
- Ph.D., Electrical Engineering - University of Washington, Seattle, WA
Supporting High-Performance Pipelined Computation in Commodity-Style FPGAs
Advisor - Scott Hauck
- M.S., Electrical Engineering - University of Washington, Seattle, WA
RaPiD AES: Developing an Encryption-Specific FPGA Architecture
Advisor - Scott Hauck
- B.S., Computer Engineering - Northwestern University, Evanston, IL
CAD Algorithms for Pipelined Netlists
Heavily registered applications confuse classical FPGA packing, retiming, placement, and routing tools. We investigated the causes of these troubles and proposed new timing-driven, register-aware approaches. The CAD portion of my dissertation shows how these tools can relate to each other.
- Provisional US Patent #4178-Inv-0001P.1USPRO, Enhancing Timing-Driven Placement
- K. Eguro and S. Hauck "Simultaneous Retiming and Placement for Pipelined Netlists", IEEE Symposium on Field-Programmable Custom Computing Machines, 2008, 139-48.
- K. Eguro and S. Hauck, "Enhancing Timing-Driven FPGA Placement for Pipelined Netlists", Design Automation Conference, 2008, 34-7.
- K. Eguro, "Supporting Heavily Pipelined Reconfigurable Computing on Commodity Devices", SIGDA Ph.D. Forum at Design Automation Conference, 2006.
- K. Eguro and S. Hauck, "Armada: Timing-Driven Pipeline-Aware Routing for FPGAs", ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2006, 169-78.
The adaptability of FPGAs make them very attractive for use in many types of hardware systems. However, the overhead required to implement this flexibility is a source of area/power/performance penalties. Can we reduce this overhead by looking at the applications we expect run on the FPGA and specialize the architecture for these domains?
- S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, A. Sharma, "Totem: Domain-Specific Reconfigurable Logic", University of Washington, Dept. of EE Technical Report, 2006.
- K. Eguro and S. Hauck, "Resource Allocation for Coarse Grain FPGA Development", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 24, No. 10, Oct 2005, 1572-81.
- K. Eguro and S. Hauck, "Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development", IEEE Symposium on Field-Programmable Custom Computing Machines, 2003, 111-20.
- K. Eguro and S. Hauck, "Decipher: Architecture Development of Reconfigurable Encryption Hardware", University of Washington, Dept. of EE, Technical Report, 2002.
- K. Eguro and S. Hauck, "synFPGA: Application Specific FPGA Synthesis", Northwestern University, Dept. of ECE Technical Report, 2000.
Classical placement algorithms for both standard VLSI and FPGA designs rely heavily on total wirelength cost. However, this cost model cannot account for routing congestion or asymmetry in routing resources. In somewhat of a chicken & egg problem, system designers only develop very specific (and potentially wasteful) types of architectures - mislead by the results of insufficient CAD tools. We investigated possible ways to fix these issues.
- K. Eguro, S. Hauck and A. Sharma, "Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement", Design Automation Conference, 2005, 439-44.
- K. Eguro and S. Hauck, "Issues of Wirelength Cost Models in Routing-Constrained FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-2004-0006, 2004.
- M. Wang, X. Yang, K. Eguro, and M. Sarrafzadeh, "Multi-Center Congestion Minimization during Placement", ACM International Symposium on Physical Design, 2000, 147-52.
Fast FPGA CAD
The compilation process to produce FPGA circuits is often very time consuming. For certain types of applications and for very large designs, conventional tools can simply be too slow. We looked at various ways to speed the process.
- K. Eguro and S. Hauck, "Fast Compilation Techniques" In S. Hauck and A. Dehon (Eds.) Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann/Elsevier, 2008
- X. Yang, M. Wang, K. Eguro, and M. Sarrafzadeh, "A Snap-On Placement Tool", ACM International Symposium on Physical Design, 2000, 153-58.