I am a Senior Research Hardware Design Engineer in the Microsoft Research Technologies (MSR-T) lab (formerly the eXtreme Computing Group (XCG)). My research interests focus on accelerating data center applications with novel hardware such as FPGAs, and on the design of energy-efficient computer architectures. At data center scales, every detail matters, and every improvement (and mistake) is magnified by orders-of-magnitude.
My research runs the spectrum from the blue-skies exploration to nitty-gritty, practical engineering. I strongly believe in seeing promising research through to prototypes and possibly even production. I love to build hardware and systems, and through building I uncover answers to hidden problems -- such as cost, power, and reliability -- which conventional research cannot always address but that are critical to turning research into reality.
In the past few years I've developed customized computing architectures for FPGAs, written compilers and assemblers for those architectures, and handled board design, manufacturing, and testing. I've partnered with numerous research and product groups, both internal and external to Microsoft, to identify and solve tough and important problems that can't be solved by incremental improvements.
Undergraduate: Dual B.A/B.S. in Electrical Engineering, Computer Science, and Physics (Triple Major) from the University of San Diego in 2003
Graduate: M.S. and Ph.D. in Computer Science & Engineering from the University of Washington in 2006 and 2009 respectively. Advisors: Susan Eggers and Mark Oskin.
- Thomas Pöppelmann, Michael Naehrig, Andrew Putnam, and Adrián Macías, Accelerating Homomorphic Evaluation on Reconfigurable Hardware, in Cryptographic Hardware and Embedded Systems - CHES 2015 - 17th International Workshop, Saint-Malo, France, September 13-16, 2015, Proceedings, Springer, September 2015.
- Andrew Putnam, Adrian Caulfield, Eric Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, Jim Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, and Doug Burger, A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services, in 41st Annual International Symposium on Computer Architecture (ISCA), June 2014.
- Behnam Robatmili, Dong Li, Hadi Esmaeilzadeh, Sibi Govindan, Aaron Smith, Andrew Putnam, Doug Burger, and Stephen Keckler, How to Implement Effective Prediction and Forwarding for Fusable Dynamic Multicore Architectures, in 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2013.
- Jonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Dan Shumow, Vinod Vaikuntanathan, and Timothy Sherwood, Inspection Resistant Memory: Architectural Support for Security from Physical Examination, in Proceedings of ISCA 2012., ISCA, June 2012.
- Manuel Saldaña, Arun Patel, Christopher Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, and Andrew Putnam, MPI As a Programming Model for High-Performance Reconfigurable Computers, in ACM Trans. Reconfigurable Technol. Syst., vol. 3, no. 4, pp. 22:1–22:29, ACM, New York, NY, USA, November 2010.
- Andrew Putnam, Aaron Smith, and Doug Burger, Dynamic Vectorization in the E2 Dynamic Multicore System, in 1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies, June 2010.
- Andrew Putnam, Susan Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, and Ralph Wittig, Performance and Power of Cache-based Reconfigurable Computing, in Proceedings of the 36th Annual International Symposium on Computer Architecture, ACM, New York, NY, USA, 2009.
- M. Saldana, A. Patel, C. Madill, D. Nunes, Danyao Wang, H. Styles, A. Putnam, Ralph Wittig, and P. Chow, MPI as an abstraction for software-hardware interaction for HPRCs, in High-Performance Reconfigurable Computing Technology and Applications, 2008. HPRCTA 2008. Second International Workshop on, November 2008.
- A. Putnam, D. Bennett, E. Dellinger, J. Mason, P. Sundararajan, and S. Eggers, CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures, in Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on, September 2008.
- Steven Swanson, Andrew Schwerin, Martha Mercaldi, Andrew Petersen, Andrew Putnam, Ken Michelson, Mark Oskin, and Susan J. Eggers, The WaveScalar Architecture, in ACM Trans. Comput. Syst., vol. 25, no. 2, pp. 4:1–4:54, ACM, New York, NY, USA, May 2007.