Share on Facebook Tweet on Twitter Share on LinkedIn Share by email
BEE3: Putting the Buzz Back into Computer Architecture
By Rob Knies
March 4, 2008 11:01 AM PT

There was a time, years ago, when computer architecture was a most exciting area to explore. Talented, young computer scientists labored on the digital frontier to devise the optimal design, structure, and implementation of computer systems. The crux of that work led directly to the PC revolution from which hundreds of millions benefit today. Computer architecture was sexy.

These days? Not so much. But Chuck Thacker aims to change that.

Thacker, a Microsoft technical fellow regarded as a pioneer in the computing industry, is working with colleague John Davis to build a hardware platform called BEE3, designed to return architecture to the cutting edge of computer-science research.

“I was in computer-architecture research for several decades and built a number of interesting computer systems,” says Thacker, who in the 1970s and early ’80s led hardware development for the Computer Science Laboratory at Xerox’s renowned Palo Alto Research Center. “But you can’t really do that anymore, because you have to design chips, and it’s just too expensive.”

In addition, simulation techniques became too slow to enable full-system experiments using real software. As time went on, interest in computer architecture began to dwindle. Those projects and papers that were devoted to the area were increasingly focused on small, incremental advances. Relevant research slowed to a crawl.

“You can count the number of people in academia today who actually do chip building,” Thacker says, “on the fingers of one hand.”

Thus, the BEE3 mission: Change the game.

BEE3, engineered by Celestica, a leading manufacturing firm, employs field-programmable gate arrays (FPGAs), semiconductors with programmable logic components, along with 64 gigabytes of DDR2 DRAM memory and a variety of high-bandwidth interfaces, all combined in a chassis that looks like a computer but is in fact a platform to emulate architectures and changes to standard architectures.

John Davis and Chuck Thacker work on BEE3
John Davis (left) and Chuck Thacker of Microsoft Research Silicon Valley collaborate on the BEE3 computer-architecture hardware platform.

“If you want to try out a new architecture or a new feature,” Thacker says, “it’s very difficult to do these days, because you have to actually build chips to build anything of substantial size. Using FPGAs, you don’t have to build chips. You can design the thing and load the FPGA with some bytes that tell it what it’s supposed to do logically.”

At that point, hardware once again begins to play a significant role in computer-architecture research.

“This is a very exciting opportunity,” says Davis, a research hardware-design engineer based, like Thacker, at Microsoft Research Silicon Valley, “especially in the academic research arena, which has been missing because it is so expensive to build chips from an actual real-cost standpoint.”

Hence, the rationale for the BEE3 project—or at least part of it.

“The project was set up for two reasons,” Thacker says. “One is to help the university community, which is one of the things we try to do a lot here in Microsoft Research. The other was that we want the machines for our own research.”

The timing is right because of the increasing maturity of FPGAs.

“They are now large enough and design tools are good enough that you can build very complex things,” Thacker states. “You can use them both for architectural experimentation and for accelerating a CPU for algorithms that don’t fit very well into [sequential] architecture.”

The viability of the FPGA approach was demonstrated last summer, when Zhangxi Tan, then an intern at Microsoft Research Silicon Valley, built a system for solving the problem of binary satisfiability, commonly used in design automation.

“He got much faster speed than what a computer could do,” Thacker reports, “because the algorithm is exactly suited for what can be done in FPGAs.”

Indeed, speed and power are the two attributes Thacker hopes the BEE3 system can help address.

“One of the big problems that we face as a company is that it’s become increasingly clear that processors aren’t going to get faster,” he says. “They dissipate too much power now, and it’s a real challenge to get rid of it. We want to look at some of these new architectures as possibilities for solving those two problems, the speed problem and the power problem.”

And Thacker and Davis have specific ideas on how BEE3 could help.

“We want to try some new techniques in internal communication within a multicore processor,” Thacker says. “In particular, we have some ideas for how to do the switch networks on such a chip and on how to use message passing as something that is available directly to programs.

“One of the nice things about these systems is that they can be very intricately instrumented, so we can get a lot of data.”

That instrumentation is an area in which Davis can help. He began working with Thacker about a year ago upon joining Microsoft Research, having developed a similar type of board as part of his Ph.D. thesis project, making him a natural to step into a project like BEE3.

“Chuck and I work together on all the aspects of the board and related gateware,” Davis says, “while interacting with our partners in terms of the prototype board manufacturing.”

The BEE3 name, incidentally, stands for the Berkeley Emulation Engine, version 3. Its predecessors, BEE and BEE2, were designed by the University of California’s Berkeley Wireless Research Center, and Thacker had used FPGAs for some projects while working at the Systems Research Center at Digital Equipment Corp before joining Microsoft Research. At the time, though, FPGAs were not sufficiently mature for the kind of architectural use BEE3 enables.

The academic connection is significant, because not only is Microsoft Research working with a variety of academic and industrial partners on BEE3, but academia also stands to be one of the prime beneficiaries. The hardware platform will be shared with academic researchers performing computer-architecture research.

“These things always go better if there are more people using them,” Thacker explains. “We decided that in order to actually benefit the way computer-architecture research is done, it would be better to just share this.”

Celestica provided the board layout and fabrication.

“The actual engineering effort … they did the schematic, the layout, the routing,” Davis says. “They’ve been a great help.”

As it turns out, there are real benefits in working with a professional hardware firm, as opposed to having the work done by academic partners.

“If you do a large-scale design like this with graduate students,” Thacker says, “you don’t get an optimal result, because it’s typically their first design. They spend a long time mastering the design tools, and they just don’t know the tricks that a professional board designer knows.

“This isn’t a matter of graduate students being dumb. They’re very smart. It’s just that, No. 1, they’re inexperienced, and No. 2, it’s not really good pedagogy, because they spend a lot of time doing the design, and as a result, they don’t have a very broad education when they graduate. I said at the beginning of the project that it was likely that the pros could get something that is half the cost and considerably more reliable in half the time, and it’s worked out that way exactly.”

Academia will, though, play a key role in BEE3’s future success. Thacker and Davis have worked closely with researchers from the University of California, Berkeley, which started the Research Accelerator for Multiple Processors (RAMP) consortium, along with the Massachusetts Institute of Technology, Stanford University, Carnegie Mellon University, the University of Texas at Austin, and the University of Washington. RAMP will provide the conduit by which BEE3 can be shared with the academic community.

“It’s six universities working together,” Davis says, “with the goal of enabling large-scale multiprocessor research.”

Other partners are contributing to BEE3, as well. Function Engineering, of Palo Alto, Calif., performed thermal modeling to ensure that the airflow in the hardware was working appropriately.

“They designed the case of the system,” Thacker says. “They designed the heat sinks for the FPGAs and did all the computational fluid-dynamic modeling to make sure that it would all work. That is one of the largest mistakes you can make in designing a computer system, to get the thermal properties wrong, because then it overheats and doesn’t work. Function was enormously helpful in this area.”

Xilinx, of San José, Calif., manufactures the FPGAs themselves, the chips and the tools to design them.

BEE3 board labeled
The BEE3 hardware with components labeled. The Virtex 5 LX110T components are the platform's field-programmable gate arrays.

But Celestica has been the most significant partner in bringing BEE3 to fruition. Celestica had the design expertise. Microsoft was interested in the potential of such a hardware platform, not in providing the hardware itself.

“Celestica has reduced a lot of the complexity in terms of the actual board design and the resulting prototypes, which were fabulous,” Davis reports. “When we got them back, within a couple of days, we had test software and processors in the FPGAs up and running.”

It’s an unusual project for Celestica, Thacker notes, but the firm’s close relationship with Microsoft didn’t hurt. Celestica is a major manufacturer of Xbox 360 consoles.

“Celestica would not normally take something like this on,” Thacker observes, “because when they do engineering, they want to have a large manufacturing follow-on. But our business relationship with them is already very, very deep. They were willing to do it for us because they found it an interesting project.”

They will get the satisfaction, however, of helping ensure that BEE3 is tangible and provides immediate value.

“The system essentially works,” Thacker says. “We found one problem in the original board design and are having it redesigned, at which point we will transition it into production and we will start using it in our own research. Up until now, this has been a project in infrastructure development, not actual research, but now we can actually begin to use it.”

That prospect has Thacker and Davis enthused.

“The coolest part of this project,” Davis says, “is the board design actually is better than the devices that are on it. We’re actually able to look at signals at a higher frequency than the FPGAs are supposed to operate at, and that’s pretty exciting.

“With this platform, you’re able to validate your work and enable technology transfer from academia to industry much, much quicker. That’s a very exciting place to be.”

For Thacker, the excitement lies in the prospect of returning computer architecture to an esteemed place at the forefront of computer science.

“We want,” he says, “to revitalize computer-architecture research.”