Our group's mission is to conduct fundamental research in computer architecture and hardware/software interaction. We explore novel architectural techniques to improve the performance, efficiency, dependability, and scalability of processor architectures and the software running on them. We are especially interested in understanding and improving the interactions between hardware and software.

Projects

• MS-ManiC: Scalable Memory Systems for Many Core Architectures
• Architectural Support for Object-Oriented Languages and Managed Runtime Systems
• High-Performance and Bandwidth-Efficient Memory Systems
• Architectural Support for Operating Systems
• Hardware Support for Memory Safety
• Energy-Efficient Microarchitectures
• Quality-of-Service Aware Microarchitectures

Publications

• Thomas Moscibroda and Onur Mutlu,
  "Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers"
  Proceedings of the 27th Symposium on Principles of Distributed Computing (PODC), pages 365-374, Toronto, ON, Canada, August 2008. Slides (pptx)
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch-Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
  to appear in Proceedings of the 35th Annual IEEE/ACM International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
• Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana,
  "Self Optimizing Memory Controllers: A Reinforcement Learning Approach"
  to appear in Proceedings of the 35th International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008.
• José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt,
  "Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps"
  to appear in Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Seattle, WA, March 2008.
• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "Performance-Aware Speculation Control Using Wrong Path Usefulness Prediction"
  to appear in Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), Salt Lake City, UT, February 2008.
• Onur Mutlu and Thomas Moscibroda,
  "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors"
  to appear in Proceedings of the 40th International Symposium on Microarchitecture (MICRO), Chicago, IL, December 2007.
• Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco,
  "Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation"
  to appear in Proceedings of the 40th International Symposium on Microarchitecture (MICRO), Chicago, IL, December 2007.
• Thomas Moscibroda and Onur Mutlu,
  "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
  Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007.
• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
  Proceedings of the 34th International Symposium on Computer Architecture (ISCA), pages 424-435, San Diego, CA, June 2007.
• José A. Joao, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Dynamic Predication of Indirect Jumps"
  IEEE Computer Architecture Letters (CAL), Vol. 6, May 2007.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors"
  to appear in Proceedings of the 5th International Symposium on Code Generation and Optimization (CGO), San Jose, CA, March 2007.
• Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
  to appear in Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), Phoenix, AZ, February 2007.
  One of the five papers nominated for the Best Paper Award by the Program Committee.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication"
  IEEE Micro, Special Issue: Micro's Top Picks from 2006 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 27, No. 1, pages 94-104, January/February 2007.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths"
  to appear in Proceedings of the 39th International Symposium on Microarchitecture (MICRO), Orlando, FL, December 2006.
  One of the 11 computer architecture papers of 2006 selected as Top Picks by IEEE Micro.
  Nominated for the Best Paper Award at MICRO-39.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
  IEEE Transactions on Computers (TC), Vol. 55, No. 12, pages 1491-1508, December 2006.

Technical Reports

• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
  HPS Technical Report, TR-HPS-2007-002, March 2007.
• Thomas Moscibroda and Onur Mutlu,
  "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
  Microsoft Research Technical Report, MSR-TR-2007-15, February 2007.
• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "A Performance-Aware Speculation Control Technique Using Wrong Path Usefulness Prediction"
  HPS Technical Report, TR-HPS-2006-010, December 2006.