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New Directions in Computer Architecture

1st Workshop on New Directions in Computer Architecture

Held in conjunction with the 42nd 2009 International Symposium on Microarchitecture (MICRO-42)

New York, New York - December 13, 2009, 8:30 am - 5:00 pm



Workshop Organizers

  • Doug Burger, MSR
  • Engin Ipek, U. Rochester

Important Dates

  • Abstracts: November 16, 2009
  • Notification: November 30, 2009
  • Final abstracts: December 7, 2009

Workshop Summary

The last five years have witnessed a dramatic shift of focus toward multicore systems in both the microprocessor industry and the architecture research community. Due in large part to power and complexity limitations to single-core scaling, multicore architectures have emerged as the primary mechanism to reap the benefits of Moore's Law in the billion-transistor era. The challenge of parallelizing sequential code bases, and the architectural support needed to facilitate that conversion, have been rightly identified as grand challenge problems. However, equally pressing challenges are looming on the near horizon, including worsening power efficiency constraints that will plague general-purpose systems as well as extreme process variation in sub-22 nm processes, which may put an end to multicore scaling as well as potentially forcing an economic end to Mooreʼs Law. In addition to the challenges posted by asymmetric device scaling, the move to data center and mobile computing is likely to change the requirements for traditional architectures radically. The goal of the “New Directions in Computer Architecture” workshop is to bring together top researchers in the community for a day of presentations and discussions about what the future of the technology is likely to hold, and in what new areas the research community, including the funding agencies, should be investing. The workshop will produce a white paper that will be published and also be disseminated to the funding agencies.

Submitting final presentations:

PDF of workshop program is here.

Workshop Schedule:

8:00 - 8:30      Breakfast

8:30 - 8:45      Welcome and introduction        Doug Burger & Engin Ipek, Workshop Chairs

8:45 - 9:45      Keynote                                       Subramanian S. Iyer, Chief Technologist, IBM Systems and Technology Group

9:45 - 10:00     Break

10:00 - 12:00   Session I: Energy-Centric Computing

        10:00 - 10:30     Reconfigurable Logic: The Future Direction of Computer Architecture

                                 Joel S. Emer, Angshuman Parashar, Tao Wang, and Azam Barkatullah

        10:30 - 11:00     Energy-Centric Computing & Computer Architecture

                                Babak Falsafi

        11:00 - 11:30     Overcoming Moore's Curse: Techniques for Powering Large Transistor Counts in Sub-45nm Technologies

                                Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge

        11:30 - 12:00     The Enabling Architecture Paradigm for Power Efficient Electronics

                                Kin Cheung, John Suehle, and William Tonti

12:00 - 1:00       Lunch

1:00 - 3:00         Session II: Approximate Accelerators

        1:00 - 1:30         ANNs as Efficient and Robust Accelerators for Emerging Applications

                                Olivier Temam

        1:30 - 2:00         Power-Efficient Computing through Approximations and Morphic Primitives for Future Teraflops Workloads

                                 Nam Sung Kim

        2:00 - 2:30         Continuous Computer Architectures

                                 Simha Sethumadhavan

        2:30 - 3:00         Leveraging Progress in Neurobiology for Computing Systems

                                 Atif Hashmi, Hugues Berry, Olivier Temam, and Mikko Lipasti

3:00 - 3:15     Break

3:15 - 5:15     Session III: Parallelism and Specialization

        3:15 - 3:45         Making Every Switch Count: Exploiting Specialization to Overcome the Power-Wall

                                 Michael Lyons, Gu-Yeon Wei, and David Brooks

         3:45 - 4:15        Low-Power Scientific Computing

                                Ganesh Dasika, Ankit Sethia, Trevor Mudge, and Scott Mahlke

         4:15 - 4:45        Adaptable Support for Programming Models in Many-core Architectures

                                Morten S. Rasmussen, Sven Karlsson, and Jens Sparsø

         4:45 - 5:15        Semantic Information Driven Speculative Execution

                                 András Vajda, Per Stenström

5:15 - 5:30     Summary, discussion, and next steps


Sponsored by the IEEE Technical Activities NTDC (New Technology Directions Committee, and Microsoft Research