This is a bus-mastering PCIe FPGA design for the Xilinx ML605 development board that acts as an interface between a PC host's main memory and the DDR3 SODIMM on the ML605 board. An accompanying WDM driver and test application demonstrate how to access the hardware and provide speed and memory tests running at up to 1.5 gigabytes per second. The accompanying paper may be found in the proceedings of FPL 2012.