The Speedy DDR2 controller is intended as an improvement on the Xilinx MIG controller for Virtex 5 FPGAs. Designed entirely from scratch on the ML505 development board, it achieves better performance at the same clock rate than the MIG controller while consuming comparable resources. The tight timing constraints imposed by high-speed DDR2 clash with the worst-case timing constraint style of FPGA design in a way that presents unique challenges. This paper discusses the primary design problems resulting from that paradox and contrasts approaches to their solutions. Performance then is compared between the Speedy DDR2 controller and the Xilinx MIG controller. The source code has been written to be more readable, maintainable, and modifiable than the MIG design and is freely downloadable from the Web.
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