DDR2 DRAM Controller for BEE3

The distribution consists of: 1) a document describing the design; 2) all Verilog source-code modules required to build the design; 3) a subdirectory containing an assembler for the TC5 RISC processor that is part of the design. This is a Visual Studio C# program; 4) a Xilinx ISE Project File that builds the design; and 5) a Readme.txt file that describes how to install and use the design.

Download details

File Name DDRCHv11.zip
Version 1.1
Date Published 25 November 2008
Download Size 0.63 MB

Note By installing, copying, or otherwise using this software, you agree to be bound by the terms of its license. Read the license.