DDR2 DRAM Controller for BEE3
The distribution consists of: 1) a document describing the design; 2) all Verilog source-code modules required to build the design; 3) a subdirectory containing an assembler for the TC5 RISC processor that is part of the design. This is a Visual Studio C# program; 4) a Xilinx ISE Project File that builds the design; and 5) a Readme.txt file that describes how to install and use the design.
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