Automated FPGA Verification and Debugging

Hardware simulations on FPGAs run more than three orders of magnitude faster than software simulations, but with much lower visibility into the circuit under test. To expedite the task of debugging and specification verification, we introduce a framework that automates many of the tedious aspects of the process. We provide tools to mine assertions either from simulation or hardware traces, to generate assertion checking engines implemented as efficient Verilog state machines, to rewrite the user’s Verilog code inserting probes to the relevant signals, and to dynamically vary the operating frequency of the circuit under test. During synthesis, we ensure that the layout of the original design is preserved as much as possible by automatically generating placement constraints, and thereby avoiding the uncertainty introduced by other on-chip debugging techniques. We give a demo of our tools using SIRC (Simple Interface for Reconfigurable Computing http://research.microsoft.com/en-us/downloads/d335458e-c241-4845-b0ef-c587c8d29796/ ) as our test circuit.

This is joint work with Kenneth McMillan and Wenchao Li.