TALK 1: RAMP: A Research Accelerator for Multiple Processors; John Wawrzynek TALK 2: Electronic system design in the late and post silicon era; Jan Rabaey

TALK 1:
The Research Accelerator for Multiple Processors (RAMP) is an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to coherent caches to networks, is implemented in field-programmable gate arrays (FPGAs) for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, assembled and run. By using hardware rather than simulation, RAMP is fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP runs full, unmodified software stacks. RAMP’s intended audience includes anyone designing and using multiprocessor systems, including architect researchers, software developers, and end users. In this talk, I will describe the background and current state of the RAMP platform development and related projects using the underlying FPGA platform.

TALK 2:
Scaling of silicon integrated technology into the deep sub-100 nm space brings with it a number of formidable challenges to the designer. Issues such as design complexity, power dissipation, process variability and reliability are challenging the traditional design methodologies. In this presentation, it is conjectured that the only viable long-term solution to these challenges is to drastically revise the way we do design, and a roadmap of potential solutions is presented. Massively parallel, error-resilient architectures potentially combined with new models of computation and communication are on the horizon. Ultimately, these innovative design solutions will help to pave the way to the post-silicon era. The presentation will be illustrated with examples of research performed at the GigaScale Systems Research Center (GSRC).

Speaker Details

John Wawrzynek is a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley, where he teaches courses in computer architecture and VLSI system design. He holds a Ph.D. in Computer Science from the California Institute of Technology and a Masters of Science in Electrical Engineering from the University of Illinois, Urbana/Champaign. He is currently co-director of the Berkeley Wireless Research Center and principle investigator of the RAMP project.

Jan M. Rabaey is the Donald O. Pederson Distinguished Professor in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. His current research interests include the conception and implementation of next-generation integrated wireless systems. This includes the analysis and optimization of communication algorithms and networking protocols, the study of low-energy implementation architectures and circuits, and the supporting design automation environments.He received the EE and PhD degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium. From 1983 till 1985, he was connected to the University of California, Berkeley as a Visiting Research Engineer. From 1985 till 1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley. He served as associate chair of the EE department from 1999 until 2002. He is currently the director of the MARCO Gigascale Systems Research Center (GSRC) as well as scientific co-director of the Berkeley Wireless Research Center. He is a Fellow of the IEEE.

Date:
Speakers:
John Wawrzynek and Jan M. Rabaey
Affiliation:
University of California, Berkeley