Candidate Talk: Statistical Inference for Efficient Microarchitectural Analysis

The transition to multi-core computer architectures expands the space of viable core designs (e.g., small, simple cores become feasible) and requires sophisticated optimization over multiple design metrics (e.g., latency, throughput, power, temperature). However, microarchitectural design space exploration is often inefficient and ad hoc due to the significant computational costs of hardware simulators. We must urgently mitigate these costs as the computer industry moves into previously unexplored domains where designer intuition is less effective and more robust analysis is necessary.

I present the case for statistical inference in microarchitectural design, enabling qualitatively new capabilities in analysis and optimization. I propose a hardware simulation paradigm that (1) defines a comprehensive design space, (2) simulates sparse samples from that space, and (3) derives inferential, non-parametric regression models to reveal salient trends. These regression models accurately capture performance and power associations for comprehensive, multi-billion point design spaces. Moreover, they can provide hundreds of predictions per second. Used as computationally efficient surrogates for detailed simulation, regression models enable previously intractable analyses of energy efficiency for emerging design priorities, including heterogeneous multiprocessors and adaptive microarchitectures.