Share on Facebook Tweet on Twitter Share on LinkedIn Share by email
Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation

José Renau, James Tuck, Wei Liu, Luís Ceze, Karin Strauss, and Josep Torrellas

Abstract

Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must exploit multiple sources of speculative task-level parallelism, including any nesting levels of both subroutines and loop iterations. Unfortunately, these environments are hard to support in decentralized CMP hardware: since tasks are spawned out-of-order and unpredictably, maintaining key TLS basics such as task ordering and efficient resource allocation is challenging.

While the concept of out-of-order spawning is not new, this paper is the first to propose a set of microarchitectural mechanisms that, altogether, fundamentally enable fast TLS with out-of-order spawn in a CMP. Moreover, we develop a fully-automated TLS compiler for aggressive out-of-order spawn. With our mechanisms, a TLS CMP with four 4-issue cores achieves an average speedup of 1.30 for full SPECint 2000 applications; the corresponding speedup for in-orderonly spawn is 1.04. Overall, our mechanisms unlock the potential of TLS for the toughest applications.

Details

Publication typeProceedings
Published inICS 2005 (International Conference on Supercomputing)
PublisherAssociation for Computing Machinery, Inc.
> Publications > Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation