Architecting Phase Change Memory as a Scalable DRAM Alternative

Memory technology scaling is in jeopardy as charge storage and sensing mechanisms becomes less reliable for prevalent memory technologies, such as Flash and DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. At present technology nodes, PCM is architected as a Flash replacement. However, to exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.

Crafted from a fundamental understanding of PCM technology parameters, we propose area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance. Collectively, these results indicate PCM is viable as a scalable alternative to DRAM.

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In  International Symposium on Computer Architecture (ISCA)

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