John D. Davis, James Laudon, and Kunle Olukotun
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use area models based on SPARC processors incorporating these architectural features. We examine CMTs with in-order scalar processor cores, 2-way or 4-way in-order superscalar cores, private primary instruction and data caches, and a shared secondary cache. We explore a large design space, ranging from processor-intensive to cache-intensive CMTs. We use SPEC JBB2000, TPCC, TPC-W, and XML Test to demonstrate that the scalar simple-core CMTs do a better job of addressing the problems of low instruction-level parallelism and high cache miss rates that dominate web-service middleware and online transaction processing applications. For the best overall CMT performance, smaller cores with lower performance, so called “mediocre” cores, maximize the total number of CMT cores and outperform CMTs built from larger, higher performance cores.
|Published in||The 14th International Conference on Parallel Architectures and Compilation Techniques|
|Publisher||Institute of Electrical and Electronics Engineers, Inc.|
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