MIPS-to-Verilog, Hardware Compilation for the eMIPS Processor

MSR-TR-2007-127 |

The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. The design constitutes an Extension for the eMIPS processor, a dynamically extensible processor realized on the Virtex-4 XC4LX25 FPGA. The Extension interacts closely with the basic pipeline of the microprocessor and recognizes special Extension Instructions, instructions that are not part of the basic MIPS ISA. Each instruction is semantically equivalent to one or more blocks of MIPS code. The purpose of the M2V compiler is to automate the process of creating Extensions for the specific purpose of accelerating the execution of software programs. M2V is a three-pass compiler that accepts as input basic blocks in the form generated by the eMIPS BBTools, a set of programs for the analysis and instrumentation of MIPS ELF images. Pass 1 of M2V generates a circuit graph that is semantically equivalent to the basic block that is being accelerated. Pass 2 schedules the operations in the circuit graph under the microarchitectural constraints of the eMIPS processor. Pass 3 emits synthesizable Verilog that constitutes the hardware accelerator that runs in the eMIPS extension slot. The compiler was implemented from scratch in C++ and despite its current limitations it can already compile a few simple examples. The quality of the synthesizable Verilog that is generated by M2V compares favorably with hand-generated code for the same input. On a 64-bit division test M2V generates an Extension that performs at the same speed but uses half the area of the handgenerated version.