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Extensible On-Chip Peripherals

Bharat Sukhwani, Alessandro Forin, and Richard Neil Pittman

Abstract

This document describes the I/O subsystem of the eMIPS dynamically self-extensible processor. This processor, during execution, can load additional logic blocks that can perform a variety of functions from adding new instructions to the base instruction set to controlling I/O pins. A dynamically loaded logic block that acts as an I/O peripheral to software is what we term an Extensible I/O Peripheral. On eMIPS, the type, number and memory space allocation of on-chip peripherals is known only at runtime, when it can change dynamically with the loading and unloading of processor Extensions. We have added to the eMIPS design additional mechanisms for a newly loaded Extensible On-Chip Peripheral to connect to the memory controller, to disconnect from it, to interact with system software in the discovery process, and to obtain the I/O space and interrupt resources that it needs to operate correctly. A general purpose operating system running on eMIPS is able to verify the security level of any processor Extension before it is enabled. Because it only executes in the address space of the application that uses it, other applications are insulated against potentially malicious Extensions. We have extended the security model to Extensible On-Chip Peripheral and their software drivers. Privileged peripherals can request access to additional interface signals that are not normally available to nonprivileged Extensions. These signals allow access to physical memory, interrupt lines and I/O pins. Extensible On-Chip Peripherals can interact with system software via memory-mapped I/O. But they can also add new I/O instructions to the processor. For instance, atomic multi-register data transfers can simplify the interaction between software and interrupt routines, especially on multi-core systems.

Details

Publication typeTechReport
NumberMSR-TR-2007-120
Pages12
InstitutionMicrosoft Research
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