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A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer

Joo-Young Kim, Scott Hauck, and Doug Burger


Data compression is crucial in large-scale storage servers to save both storage and network bandwidth, but it suffers from high computational cost. In this work, we present a high throughput FPGA based compressor as a PCIe accelerator to achieve CPU resource saving and high power efficiency. The proposed compressor is differentiated from previous hardware compressors by the following features:

  1. Targeting Xpress9 algorithm, whose compression quality is comparable to the best Gzip implementation (level 9);
  2. A scalable multi-engine architecture with various IP blocks to handle algorithmic complexity as well as to achieve high throughput;
  3. Supporting a heavily multi-threaded server environment with an asynchronous data transfer interface between the host and the accelerator.

The implemented Xpress9 compressor on Altera Stratix V GS performs 1.6-2.4Gbps throughput with 7 engines on various compression benchmarks, supporting up to 128 thread contexts.


Publication typeInproceedings
PublisherIEEE 22nd International Symposium on Field-Programmable Custom Computing Machines

Newer versions

Jeremy Fowers, Joo-Young Kim, Doug Burger, and Scott Hauck. A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs, IEEE – Institute of Electrical and Electronics Engineers, 4 May 2015.

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