Anirudh Badam, Vivek S. Pai, and David W. Nellans
Today, many system designers try to fit the entire data-set of an application in RAM to avoid the cost of accessing magnetic disk. However, for many data-centric applications this is not an option due to the capacity and high $/GB constraints of RAM. As a result, system designers are relying on NAND-Flash to augment RAM. However, rewriting the application to actively tier data between disk, RAM, and flash is a complicated process. Years of research has enabled some applications, namely databases, to tier efficiently, yet there are still large classes of applications that have no built-in tiering and a full application rewrite may take months or years. In this paper, we propose Chameleon, a system to augment RAM with NAND-Flash transparently. Chameleon removes most of the impediments to using flash via virtual memory. Chameleon is the first transparent tiering system to provide low-latency accesses to both RAM and NAND-Flash.
We show that applications using Chameleon, outperform applications using state-of-the-art tiering mechanism by providing more than two orders of magnitude improvement in latency for working sets that can fit in RAM. We also show that Chameleon provides upto 47% latency improvement for out-of-core applications. Finally, we show that Chameleon improves the flash device’s lifetime by upto 8x.
Publisher ACM SIGOPS