An Attention Controlled Multi-Core Architecture for Energy Efficient Object Recognition

In this paper, an attention controlled multi-core architecture is proposed for energy efficient object recognition. The proposed architecture employs two IP layers having different roles for energy efficient recognition processing:  the attention/control IPs compute regions-of-interest (ROIs) of the entire image and control the multiple processing cores that perform local object recognition and processing on selected area. To this end, a task manager is proposed to perform dynamic scheduling of various ROI tasks from the attention IP to multiple cores in a unit of small-sized grid-tile. Thanks to a number of grid-tile threads generated by the task manager, the utilization of multiple cores amounts to 92% on average. As a result, the proposed architecture archives 2.1 x energy reduction in multi-core recognition system by indicating processing cores to focus on critical area of the image with a 0.87 mJ attention processing. Finally, the proposed architecture is implemented in 0.13 um CMOS technology and the fabricated chip verifies 3.2 x lower energy dissipation per frame than the state-of-the-art object recognition processor.