Abstract

This report describes a method for scheduling data cell traffic through a crossbar switch in such a way as to guarantee that the time slots for each flow, and optionally for certain aggregates of flows, are approximately uniformly distributed throughout the duration of the scheduling frame. Such a “smooth” schedule achieves reductions both in the latency of data flows and in the need for associated memory buffers. Our method, called recursively balanced scheduling, can be used to compute smooth schedules even under conditions of maximum load, where the bandwidth requirements of the flows to be scheduled are sufficient to consume the entire capacity of the switch. This method has been implemented for a working high-speed ATM switching network, AN2. We describe the implementation, its performance, and possible future improvements.

Details

Publication typeManual
URLhttp://www.hpl.hp.com/techreports/Compaq-DEC/SRC-RR-150.html
NumberSRC-RR-150
InstitutionDigital Systems Research Center
AddressPalo Alto, CA
PublisherDigital Systems Research Center
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