Share on Facebook Tweet on Twitter Share on LinkedIn Share by email
Deterministic Parallel DPLL (DP2LL)

youssef hamadi, said jabbour, cedric piette, and lakhdar sais

Abstract

Parallel Satisfiability is now recognized as an important research area. The wide deployment of multicore platforms combined with the availability of open and challenging SAT instances are behind this recognition. However, the current parallel SAT solvers suffer from a non-deterministic behavior. This is the consequence of their architectures which rely on weak synchronizing in an attempt to maximize performance. This behavior is a clear downside for practitioners, who are used to both runtime and solution reproducibility. In this paper, we propose the first Deterministic Parallel DPLL engine. It is based on a state-of-the-art parallel portfolio architecture and relies on a controlled synchronizing of the different threads. Our experimental results clearly show that our approach preserves the performance of the parallel portfolio approach while ensuring full reproducibility of the results.

Details

Publication typeTechReport
NumberMSR-TR-2011-47
> Publications > Deterministic Parallel DPLL (DP2LL)