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A VLSI Design Management Environment

Steve Hodges and Peter Rounce


Advances in technology are continually increasing the number of discrete devices which may befabricated in a single integrated circuit. When we talk of VLSI chips today, they may well contain in excess of one million transistors - a figure which would have seemed almost unbelievable a few years ago. With this dramatic increase in complexity, it is more important than ever before to control the design process, thus maintaining the required quality, reliability and extensibility of a given design. Equally, speed of development in a rapidly changing market, development costs and the cost of mistakes play important parts in a commercial environment. It is becoming increasingly important that the design process is as quick as possible, as cheap as possible and that mistakes are highlighted as early as possible (certainly before fabrication). In a recent study of these problems in VLSI design, in particular with reference to the design methods and tools used in the Computer Science Department at UCL, a report was prepared, detailing the structure of a ‘Digital Design Environment’ (DDE)†. The issues brought to light by this study, and the solutions put forward are summarised below.


Publication typeInproceedings
Published inProceedings of the IEE Colloquium on "Design management environments in CAD" 1991
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