A Parameterizable Processor Architecture for Large Characteristic Pairing-Based Cryptography

Gary C.T. Chow and Ken Eguro

Abstract

Cryptographic pairing (bilinear mapping) is a core algorithm for various cryptography protocols. It is computationally expensive and inefficiently computed with general purpose processors. Although there has been previous work looking into efficient hardware designs for pairing, most of these systems use small characteristic curves which are incompatible with practical software designs. In this paper, we propose a novel processor architecture for pairing-based cryptography applications using large characteristic curves. The architec-ture is parameterizable to fields with different bit-widths and different pairing algorithms. It takes advantage of some unique FPGA features such as huge ag-gregated memory bandwidth and massively parallel computation logic to achieve high performance and high energy efficiency. An example 512-bit pairing processor with this architecture can verify 9.6K pairings/second on a Xilinx Virtex-6 FPGA. It is 18.7x faster than a single threaded software version running on a 2.5 GHz Xeon E5420 CPU. The per-pairing energy consumption of the FPGA processor is estimated to be at least 6.0x better than its CPU counterpart. The proposed architecture is ideal for server-side applications requiring flexibility, performance and energy efficiency

Details

Publication typeTechReport
NumberMSR-TR-2010-77
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