FPGA Circuit Synthesis of Accelerator Data-Parallel Programs

This paper describes the techniques used to describe and synthesize FPGA circuits expressed in a data-parallel domain specific language (DSL) called Accelerator. We identify the subset of data-parallel descriptions that are supported by our system and explain how we track memory access patterns which allow us to generate efficient FPGA circuits.

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In  FPGAs for Custom Computing Machines

Publisher  IEEE Computer Society
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