Hari Kannan, Mihai Budiu, John D. Davis, and Girish Venkataramani
We propose using a profiling-based technique (Dynamic Critical Path) to guide SoC optimization. Optimizing SoCs composed of many modules involves exploring a large space of possible configurations (exponential in the number of component modules). We present this optimization technique applied to a Globally Asynchronous Locally Synchronous (GALS) RTL design. Furthermore, we investigate the loss of precision when abstract versions of hardware modules are used for the critical path computation. Using the
critical path provides very fast convergence towards optimal or near-optimal solutions when
analyzing large configuration spaces by optimizing the design for composite optimization metrics, such as energy-delay.
|Published in||the Proceedings of the 22nd IEEE International SOC Conference (SOCC)|
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