Satnam Singh

Satnam Singh, 7 JJ Thomson Avenue, Cambridge CB3 0FB, United Kingdom Email: satnams@microsoft.com Phone: +44 1223 479905 Cell: +44 7979 648412 USA: +1 206 219 9024 WWW: http://research.microsoft.com/~satnams/

I work in the Programming Principles and Tools group at Microsoft Research in Cambridge. My research interests involve various aspects of heterogeneous manycore architectures including:

• Compiling parallel programs into digital circuits. I have been working with David Greaves at Cambridge University to explore the idea of performing hardware design with a regular parallel programming language. We are working on a system called Kiwi which transforms .NET assembly language into FPGA circuits. We have a paper Kiwi: Synthesis of FPGA Circuits from Parallel Programs which was presented at FCCM 2008.
• Programming models for reconfigurable systems. For example, my invited talk at the FPGA 2007 conference Programming Models for Parallel Systems: The Programmer's Perspective proposes that we use existing and new parallel and concurrent programming techniques as the starting point for higher level hardware descriptions. Perhaps in some cases hardware design and parallel programming are the same activity and they have become separated at birth into C and Verilog through an accident of history.
• Hardware design using synchronous languages. For example, using Esterel as described in our CPA 2007 paper Hardware/Software Synthesis and Verification using Esterel.
• Writing applications using experimental techniques for expressing parallelism and concurrency. I worked on the sorter application in the ICFP 2007 paper with Tim Harris on Feedback direct implicit parallelism. With Nalini Vasudevan and Stephen Edwards at Columbia University we have also experimented with implementing multi-way rendezvous in Haskell using software transactional memory. We have a paper at IPDPS 2008 called A Deterministic Multi-Way Rendezvous Library for Haskell.
• Producing multi-target descriptions for manycore systems. The paper Declarative Programming Techniques for Many-Core Architectures (presented at HFL 2007) demonstrates how data-parallel descriptions for high speed sorters which were originally designed for FPGAs can be re-targeted to GPUs.

Previously I worked in a group that developed the Coordination and Concurrency Runtime (CCR) which I use in my concurrency experiments. I've co-authored a paper on the CCR called An Asynchronous Messaging Library for C# which was presented at the SCOOL 05 workshop before OOPSLA 2005. I also worked on software transactional memories with Anthony Discolo, Tim Harris, Simon Marlow and Simon Peyton Jones and we wrote a paper called Lock Free Data Structures using STM in Haskell which was presented at FLOPS 2006. The paper Higher Order Combinators for Join Patterns using STM describes how to encode Comega style join patterns using software transactional memory (presented at TRANSACT 2006).

I serve on various conference programme committees including FCCM, FMCAD, DCC, and FPT. For the last three years I served as the programme chair for the system level modelling track of the Design, Automation and Test Conference. I am a member of the IFIP Working Group 2.8 on functional programming. I also taught a course on VLSI Testing at the University of Washington. I am a visiting faculty member at Chalmers.

Before joining Microsoft I was a researcher at Xilinx's labs in San Jose for seven years and before that I was a faculty member at the University of Glasgow for seven years. I have worked on the Lava system with Mary Sheeran and Koen Claessen which applies functional programming techniques to the design and analysis of high performance FPGA circuits. I have authored around 50 technical publications.

Here is a bio which can be used for presentations.